A PDF copy of this program is available. Links to the most papers and some presentations are provided below. SELSE is an informal workshop. To encourage widespread participation authors are given the option to not have their papers or presentations published on this web site. We thank all authors for their participation.
| SELSE 5 Day 1 - March 24th, 2009 Stanford University | ||||||||||||
| 8:00-8:45 | Continental Breakfast and Registration | |||||||||||
| 8:45-9:00 | Welcome and Introduction from General Co-Chair and Committee | |||||||||||
| 9:00-10:30 | Session I: System Vulnerability and Workload Effects Chair: Rakesh Kumar (UIUC) | |||||||||||
| Paper Paper Slides Paper Slides | The Effect of Input Data on Program Vulnerability. Vilas Sridharan and David Kaeli. Quantized AVF: A Means of Capturing Vulnerability Variations over Small Windows of Time. Soft Error Effect and Register Criticality Evaluations: Past, Present and Future. | |||||||||||
| 10:30-10:45 | Break | |||||||||||
| 10:45-12:15 | Session II: Applications / Case Studies Chair : Charles Recchia (Intel) | |||||||||||
| Paper n/a Slides n/a Paper Slides | Evaluation of Low-Cost Detection and Recovery of Soft Errors in an ABS controller. Daniel Skarin and Johan Karlsson A Case Study of the Soft Errors Observed in I/O Adapters. Anh Dang, Pia Sanda, Ricardo Mata and Subhasish Mitra. Platform Neutron Testing for Single Event Upset (SEU). Tsu-Yau Chuang, Eric Schmidt and Shi-Jie Wen. | |||||||||||
| 12:15-12:45 | Lunch | |||||||||||
| 12:45-14:00 | Poster Session I | |||||||||||
| Paper Paper Paper Paper Paper Paper | Adapting to Intra-Die Variations in Transient Fault Susceptibilities. Kenneth Zick and John Hayes. Testing the Critical Operating Point (COP) Hypothesis using FPGA Emulation of Timing Errors in Overscaled Soft-Processors. Thermal Management in Reliably Overclocked Systems.
Analysis of a Multiple Cell Upset Failure Model for Memories. Single-Threaded Mode AVF Prediction During Redundant Execution. Exploring the Synergy of Emerging Workloads and Silicon Reliability Trends. | |||||||||||
| 14:00-14:15 | Break | |||||||||||
| 14:15-16:15 | Session III: SER Measurement and Modeling Chair: Steve Walstra (Intel) | |||||||||||
| Paper Slides Paper Slides n/a Paper | Neutron Beam Irradiation Study of Workload Dependence of SER in a Microprocessor. Ted Hong, Sriram Narayanan, Galen Lyle, Rakesh Kumar and Douglas L. Jones. Trends from Ten Years of Soft Error Experimentation. Comparison of Alpha-particle and Neutron-induced Combinational and Sequential Logic Error Rates at the 32nm Technology Node. Soft-Error Cross-Section Mapping and Rate Prediction using Accurate Simulation. | |||||||||||
| 16:15-16:30 | Break | |||||||||||
| 16:30-17:15 | Panel: “System Specifications of Soft Error Performance”
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| 17:15-18:00 | Birds of a Feather Sessions
Birds of a Feather sessions provide small groups the opportunity to gather for a short discussion and planning meeting related to a specific topic. One session has been planned and the others will be announced by lunchtime of day 1. E-mail suggestions to publications@selse.org or speak to one of the workshop organizers onsite. | |||||||||||
| Session A: Embedded systems derating: How many soft errors lead to system failures in a small system? Studies have been published describing the derating values to use to predict the fraction of soft-errors that lead to system errors. Most of these studies have concentrated on this question using large scale computer systems that are highly optimized for soft-error tolerance. Two recent papers on embedded system derating suggest that the values are quite different for simpler microprocessor architectures. Participants will be asked to consider: Is there a real difference between these classes of systems? How should derating be defined for embedded systems? What projects or avenues of research are likely to be profitable to further investigation of this topic? | ||||||||||||
| Session B & C: TBD |
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| 18:00- | Dinner and Reception | |||||||||||
| SELSE 5 Day 2 - March 25th, 2009 Stanford University | ||||||||||||
| 7:45-8:30 | Continental Breakfast | |||||||||||
| 8:30-9:15 | Report From Birds of Feather Sessions | |||||||||||
| 9:15-10:15 | Session IV: Mitigation Techniques – Logic Chair: Charles Slayman (Sun) | |||||||||||
| Paper Slides Paper Slides | A Coarse-Grained Dynamically Reconfigurable Architecture Enabling Flexible Reliability. Dawood Alnajjar, Younghun Ko, Takashi Imagawa, Masayuki Hiromoto, Yukio Mitsuyama, Masanori Hashimoto, Hiroyuki Ochi and Takao Onoye. Fault-Tolerant Resynthesis for Dual-Output LUTs. Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He and Minming Li. | |||||||||||
| 10:15-10:30 | Break | |||||||||||
| 10:30-12:00 | Session V: Microprocessors Chair: Jim Tschanz (Intel) | |||||||||||
| Paper Paper Paper Slides | A Low-Overhead Technique to Protect the Issue Control Logic Against Soft Errors. Javier Carretero, Xavier Vera, Jaume Abella, Pedro Chaparro and Antonio González Voltage Noise: Why It’s Bad, and What To Do About It. Vijay Janapa Reddi, Meeta S. Gupta, Krishna K. Rangan, Glenn Holloway, Gu-Yeon Wei, Michael D. Smith and David Brooks A Detector for Harmful Errors. | |||||||||||
| 12:00-12:45 | Lunch | |||||||||||
| 12:45-14:00 | Poster Session II | |||||||||||
| Paper Paper Paper Paper n/a | NBTI-Aware Dynamic Instruction Scheduling. Taniya Siddiqua and Sudhanva Gurumurthi. Implementation and Validation of a Low-Cost Single-Event Latchup Mitigation Scheme. Soft-error Mitigation at the Architecture-Level Using Berger Codes and Instruction Repetition. 3D Simulation and Analysis of the Radiation Tolerance of Voltage Scaled Digital Circuits. | |||||||||||
| 14:00-14:45 Slides | Invited Talk: Helmet Puchner, Cypress Semiconductor “On The Accuracy of Accelerated and Life Soft Error Testing" | |||||||||||
| 14:45-15:00 |
Break |
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| 15:00-16:30 | Session VI: Mitigation Techniques – Arrays and Sequentials Chair: Terry Garyet (Freescale) | |||||||||||
| Paper Slides Paper Paper Slides | Soft Error Mitigation Schemes for High Performance and Aggressive Designs. Naga Durga Prasad Avirneni, Viswanathan Subramanian and Arun Somani. Protecting Prediction Arrays against Faults. Modeling SRAM Failure Rates to Enable Fast, Dense, Low-Power Caches. | |||||||||||
| 16:30-17:00 | Closing Discussion |